| 释义 |
vhdl
基本例句
n.极高密度脂蛋白
An alarm system for security guarding designed with FPGA is discussed in this thesis, and the theory and structure as wall as the design for VHDL module are also given bellow.
文中讨论利用 FPGA设计的用于安全防范的报警系统，讲述系统的原理与结构，给出 VHDL的模块设计。 cnki
From the clew of implementing a stratified, modularized and parameterized design, the thesis describes the hardware implementation of the IIR filter with VHDL and schematic diagram design method.
按照层次化、模块化、参数化的设计思路，采用VHDL硬件描述语言和原理图两种设计技术进行了 IIR滤波器的硬件设计； cnki
The reference CPU core use VHDL language input, make logic synthesis and simulation through the popular EDA tools, then it was implemented in FPGA.
CPU内核采用 VHDL硬件描述语言输入，结合流行的 EDA设计、综合、仿真工具，最后在 FPGA上实现该内核。 cnki
The circuit design of serial synchronous communication based on VHDL includes design of serial synchronous sending circuit and receiving circuit.
基于 VHDL的串行同步通信电路设计，包括串行同步发送电路和接收电路的设计。 cnki
The design of source files by VHDL, compilation and synthesis, and implementation methods with HDPLD are discussed.
着重讨论了用 VHDL设计源文件，通过综合编译，用 HDPLD实现的方法。 cnki
The design of functional module and simulation and synthesis based on FPGA by using VHDL can be realized on VGA Controller, which can display the figure, image, character and the like.
用硬件描述语言VHDL对可编程器件FPGA进行功能模块设计、仿真综合，可实现 VGA控制器显示各种图形、图像、文字等。 cnki
The FPGA design is described by VHDL and the DSP programs are designed by C and assemble language.
FPGA设计采用 VHDL语言描述， DSP程序采用了 C语言程序和汇编程序编制。 iciba
The ISE user interface allows you to add entities either in a schematic view or as HDL objects either Verilog or VHDL.
ISE用户界面允许您在示意图视图添加实体或将其作为 HDL对象 Verilog或 VHDL添加。 ibm
The logic synthesis of VHDL language is a method that the description of higher abstract hierarchy is shifted to lower one automatically.
VHDL语言的逻辑综合就是将较高抽象层次的描述自动转换到较低抽象层次描述的一种方法。 cnki
The methods to solve several problems of designing VHDL synthesis system are given in this paper.
讨论了在研究和设计 VHDL综合系统时遇到的若干问题的解决方案。 cnki
The model of RAID channel adapter de-scribed by VHDL is put forward.
提出了用硬件描述语言VHDL描述 RAID通道适配器模型。 www1.chkd.cnki.net
The Top- Down design method which use high level synthesis tools to accept VHDL as it's input is the trend of electronic design.
采用 VHDL语言输入，综合工具综合的自顶向下的设计方法是当前电子设计发展的趋势。 cnki
This paper carry out MATLAB simulation about adaptive antenna arrays of anti-jamming filtering, analysis the performance, implement the design in ISE using specific VHDL program.
本文将针对自适应天线阵抗干扰滤波算法进行描述，进行MATLAB仿真及性能分析，并在 ISE中利用 VHDL语言实现。 dictall
To design the control system of LCD, a method based on CPLD is described, including the means of designing the horizontal sync signal and the vertical sync signal with VHDL.
介绍了基于 CPLD液晶显示屏控制系统的设计方法，并详细介绍了用VHDL硬件描述语言设计行，场液晶显示时序与控制的方法。 cnki
After the hardware-software partition, the description in C language of hardware should be translated into the description in VHDL language.
语言的系统描述经过软硬件划分之后，要求将硬件实现部分转换为适合于综合的 VHDL语言。 cnki
An air-condition controller circuit was designed by use of a kind of industrial standard hardware description language called VHDL. The pro-posed function was realized through simulation.
本文利用硬件描述语言中的工业标准语言VHDL，设计了一个空调机控制器电路，并通过仿真实现了预定功能。 cnki
At last, this thesis realizes digital down converter based on FPGA, and the whole designing process includes algorithm simulation, VHDL description, FPGA simulation and real system test.
最后，基于 FPGA对数字下变频进行了设计及实现，具体包括：算法仿真、 VHDL描述、 FPGA仿真和实际系统测试。 cnki
In this paper, the optimization method was used to design the interface circuit, and use VHDL description to design low voltage digital delay timer.
在电路设计过程中，对后级接口电路进行了最优化设计，采用 VHDL描述的方式实现了低压数字延时电路模块的设计。 cnki
On the base of analyzing the structure and the design difficulty of the asymmetric synchronous FIFO, an asymmetric synchronous FIFO is achieved by using VHDL language and FPGA in this paper.
本文在分析了非对称同步 FIFO的结构特点及其设计难点的基础上，采用 VHDL描述语言，并结合 FPGA，实现了一种非对称同步 FIFO的设计。 cnki
RISC microprocessor is developed by using modular design method and VHDL language based on FPGA and EDA technology.
基于 FPGA和电子设计自动化技术。采用模块化设计的方法和 VHDL语言，设计一个基于 FPGA的 RISC微处理器。 cnki
The approach of description of finite state machine with VHDL is presented. This paper analyses the emphasises in the process of synthesis and provides the solutions.
介绍了使用 VHDL描述有限状态机的方法，重点分析了综合过程中的难点并提供了解决方法。 cnki
The course requires extensive use of VHDL for describing and implementing digital logic designs.
这课程需要使用 VHDL去描述和执行数字逻辑设计。 putclub
Therefore, the author design an anti- collision system of Type A card with VHDL, which is tested with RTL simulating.
基于此，本文使用 VHDL设计了 A型卡的防冲突电路，使用 RTL级波波形仿真验证了芯片的工作。 cnki
This article introduces VHDL which has a strong de signal function and extensive application and applies it in a concrete circuit design.
介绍 VHDL语言所具有的强大设计功能和广泛的应用领域，并将其运用于具体数字电路设计。 cnki
This article studied how to design a counter based on VHDL which will be applied in drip-irrigation controller.
本文针对 VHDL在滴灌控制器的定时器芯片的设计展开研究。 cnki
This paper will discuss the various synthesizability problems of VHDL syntax in detail.
本文详细地分析了 VHDL语言的可综合性问题。 cnki
This paper briefly introduced ISP devices and hardware description language VHDL, and designs a kind of high integrated grating digital readout based on division theory and ISP design theory.
文中将在系统可编程器件和相应的硬件描述语言 VHDL作了简要介绍，本文还详细介绍了基于锁相细分理论和 ISP设计思想的高集成度的光栅检测装置。 cnki
With growing development of the technology of integrated circuit and EDA, VHDL has become a standard IEEE's hardware description language.
随着集成电路技术和 EDA技术的不断发展， VHDL已经成为 IEEE标准化的硬件描述语言。 cnki
VHDL Intermediate Data Format VIDF is demanded by VHDL DesignEnvironment VDE. It is used as the common data interface in the various tools of the VDE.
VHDL中间数据格式 VIDF是 VHDL设计环境 VDE的要求，用来作为 VDE中各设计工具的一个公共数据界面。 cnki |