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Veris
释义
Veris
BNC¹¹⁴⁰²⁴⁺
⁵
基本
例句
韦里斯
¹⁰⁰
A solution for property verification of synchronous VHDL design is introduced, and VERIS an efficient symbolic model checker is implemented.
介绍了一个针对同步时序电路VHDL设计的性质验证的解决方案——一个有效的符号模型判别器 VERIS。
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