| 释义 |
sequential logic短语¹³¹⁶²⁰⁺³
基本例句
时序逻辑
A new method named MDS is introduced in this article since the methods of designing sequential logic circuit in fundamentals of digital electronics are not so efficient and too simple.
通用教材《数字电子技术》中介绍的传统的时序电路设计方法——状态表及状态图法过于简单，很难满足较复杂电路的设计要求。 cnki
The method of computing the fault form of sequential logic circuits is presented, and some measures of simulating faults are also given.
文章提出了加速故障表传输的方法，以及一种时序电路故障表计算的新方法。文章给出了演绎故障仿真的一般步骤。 cnki
Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock- tree.
此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。 cnki
In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock- tree.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。 cnki |