| 释义 |
PLLCOCA¹⁰³³⁰⁹BNC¹⁴⁴⁶⁶⁴⁺³
基本例句
n.锁相环路¹⁰⁰
Due to steady phase error, low-order PLL has a trouble in tracking frequency ramp signals, so that the receiver cannot lock carrier signals.
低阶锁相环跟踪频率斜升信号时产生的稳态相差致使环路失锁，接收机无法锁定载波信号。 dictall
Phase-locked loop PLL has been applied in many fields.
锁相环在很多领域都得到了广泛应用。 cnki
The merits of DDS such as super fine frequency resolution, high frequency accuracy, easy programmed can be in combination with the excellent character of narrow-band tracing filter merits of PLL.
它可以将 DDS的超高频率分辨率、高频率精确度、容易实现程控等优点与锁相环良好的窄带跟踪滤波特性相结合。 cnki
The achievement of this paper will provide lots of useful guides and references on the design of system and module level in PLL circuit, especially on the analysis and simulation of phase noise.
本论文的研究成果对于锁相环电路中的模块级设计与系统级设计，尤其是相位噪声的分析与模拟均有很好的指导意义和参考价值。 cnki
The method of improving the output signal frequency resolution and stability using PLL technique are mainly described.
重点介绍了利用锁相环技术提高输出频率的分辨率和稳定度的方法； cnki
The phase locked loop PLL frequency synthesizer for digital tuning system DTS, which is used in DTS of car radio receiver, is presented.
针对汽车音响收音数字调谐系统的实例，介绍一种广播用双波段锁相环频率合成电路的设计方法。 dictall
The system clock based on the theory of phase- locked loop PLL is a two level PLLincluding the circuit of the synchronization signals and high frequency pixel clock.
基于锁相理论的视频锁相同步系统是一个二级锁相环路，包括同步信号发生电路和高频点像素时钟电路。 cnki
A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.
设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。 dictall
Actually, the bulk of the work in determining an optimal PLL configuration is wrapped up in determining the list of all possible configurations that meet our needs.
实际上，确定 PLL最优配置的大部分工作是确定所有的满足我们需求的配置清单。21ic
Analyzing the responses of three kinds of PLL- FM ways and their stabilities.
详细分析了三种锁相调频方式的环路响应及环路稳定性。 cnki
At the same time, this topic has also designed the performance test logic for PLL according to its characteristic.
另外，本课题还根据锁相环的特点，设计了一种锁相环性能测试逻辑。 cnki
Based on signal mixed frequence, it gives a new RF signal synthesizing plan combining DDS with PLL.
提出以信号混频为基础，通过 DDS与集成锁相环 PLL技术相结合的新型射频信号合成方案。 cnki
Before we can setout to find the optimal configuration for our PLL, we need to first consider how we find any configuration for our PLL.
在我们准备为锁相环找到最优配置之前，首先要考虑如何找到锁相环的所有配置。21ic
Digital PLL frequency synthesizer is applied to produce driving signals, and the frequency-hopping circuit is designed to improve switch speed between different frequency of driving signals.
采用数字锁相环频率合成器产生射频驱动信号；设计了跳频电路部分以提高不同频率驱动信号间的切换速度； cnki
Effectively applying the technology of PLL not only enhance and improve the speed and the veracity of measurement, but also can actualize some special controlling effects.
有效地运用锁相同步技术，不仅可以提高测量的速度、改善测量的准确度，还可以实现一些特殊的控制效果。 oaps.lib.tsinghua.edu.cn
In this paper the principle and design of a microcomputer- controlled PLL frequency synthesis digit tuning system is discussed.
本文叙述了一个用微机控制的锁相环频率合成数字调谐系统的原理和设计。 cnki
In this paper, a low spurious and small step frequency synthesizer is studied on the base of the theories of DDS, PLL and the complex synthesis.
本文以 DDS、 PLL和混合频率合成技术为理论基础，对微波低杂散小步进频综的实现进行了研究。 fabiao
On the basis of orthogonal correlation, Digit correlative estimation acquisition is much shorter than conventional PLL and maximum likelihood decision correlation.
经实际验证，与以往采用的锁相环法和最大似然判决相关法相比，捕获时间明显缩短。 cnki
Some technique problems in fast frequency hopping synthesis are solved by making use of a programmable time division- fractional division PLL.
该合成器采用程控时分复用小数分频锁相技术，解决了快速跳频频率合成中的诸多固难。 cnki
Specifically, we will need to be able to find all of the possible configurations that our PLL can use for a given reference oscillator and desired output frequency.
特别是，我们需要能够找到可以用于给定参考振荡器和期望输出频率的所有可能的锁相环配置。21ic
Systematic principle analyses and simulation of PLL frequency synthesizer are carried out, a verifying circuit is designed and finished.
论文对锁相环频率合成器的设计进行了系统的理论分析和仿真，设计并完成了具体电路验证。 cnki
The ICO, modulator, transmitter, PLL, time-domain filter in the modem are also deeply discussed.
本文还对调制解调电路中的 ICO、调制器、发送器、 PLL、时域滤波器作了细致探讨。 http://dj.iciba.com
The PLL frequency synthesizing technic, which develops fast recent years, has been the main design scheme of signal source, because of its performance advantage.
近年来迅速发展的锁相环频率合成技术，以其自身性能优势，逐渐成为射频信号源的主要设计方案。 cnki
This paper discusses the influence of mixer on the phase lock-loop PLL circuit of a local oscillator.
本文讨论了采用锁相环路作为本振信号的混频器对本振锁相环路的影响。 cnki
This paper introduces mainly phase noise and its spectrum characters in pulse modulation wave, and promotes a new measurement system about phase noise using Digital PLL Phase Locked Loop.
本文着重分析了脉冲调制波的相位噪声及其功率谱，提出了一种利用数字锁相环测试相位噪声的实现技术方案。 cnki
This methodology is implemented in charge- pump PLL circuit design, the feasibility and efficiency of the method has been verified.
这种设计方法已应用于一种电荷泵锁相环电路设计中，验证了这种设计方法的可行性和有效性。 cnki |