| 释义 |
pipelined ADC
基本例句
流水线ADC
A 12-bit, 40MS/spipelined ADCis designed in this paper.本课题设计了一个12位、40MS/s流水线ADC。
This thesis describes the system design of a high-resolutionpipelined ADC.本文论述了高速高精度流水线结构模数转换器的设计。
A 10 - bit 20Mpspipelined ADCis designed, which has the merit of high speed and high resolution.设计 10位 20MpS 流水线模数转换器,它具有高速度高分辨率的优点。
The layout design of the proposedpipelined ADChas been finished and the test chip is being implemented.设计的模数转换器在0.;6um工艺下全部电路运行功耗仅为49mW;比同类电路的平均功耗要低13%;实现了低功耗的设计。
In this thesis, a low power 12bit 80MS/spipelined ADCis designed in TSMC 3.3V 1P5M 0.25um CMOS process.本文基于TSMC 3.;3V 1P5M 0
Abstract: The design of a low-voltage, high-speed operational amplifier is based on thepipelined ADC.文章摘要: 本文设计了一种基于流水线ADC系统应用的低电压、高速运算放大器，该运放使用折叠式共源共栅结构、稳定的电压偏置电路、新型的共模反馈电路，使运放达到更高的性能。 |