| 释义 |
interruption mask registerIMR /7, a 4bit hardware register with one bit corresponding to each of the 4 priority interrupt levels；each bit setting specifies whether or not interrupts are recognized on that level.；在IBM System/7中,一种4个二进制位的硬件寄存器,对应4个优先中断级。根据各位设置的状态,确定各个中断级的中断是否被认可。 |