| 释义 |
clock network
基本例句
时钟网络
A clock Network is combinational logic between a clock source and the registers in the transitive fanout of the source.时钟网络：网络是一个时钟之间的时钟源和源寄存器传递扇组合逻辑。
Amongclock networkdesigns, the buffered clock tree architecture is the most popularclock networkdesign adopted in modern VLSI designs.在时钟网路的设计中，目前最普遍采用在现今晶片设计的是缓冲器式时钟树。 |