| 释义 |
Clock gating
基本例句
时钟门控
Clock gatingis an efficient way of reducing dynamic power consumption in digital circuits.时钟闸控是降低数位电路动态功率消耗的有效方法。
It is always a good idea to invest the time at the beginning to understand the clock structure and the clock gating in your design.在设计一开始首先了解其时钟结构和门控时钟是一个不错的想法。
This paper analyses the disadvantages of many clock gating techniques and points out that they are obstacles in System-on-Chip design.门控时钟技术一直以来是降低芯片动态功耗的有效方法。
Adaptive Clock Gating Technique for Low Power IP Core Design in SoC应用于片上系统中低功耗IP核设计的自适应门控时钟技术 |