clock cycle英klɒk 'saɪkl美klɑːk 'saɪkəl短语⁷⁹⁹⁷⁸⁺⁹ 基本例句 时钟周期 The system is designed to generate one output in every clock cycle, the detail component and the approximation of the input signal are available alternately. 系统实现了每一个时钟产生一个输出，输入信号的细节分量和近似分量交替输出。 cnki